Circuit calibration using voltage injection

ABSTRACT

Efficient calibration of circuits is performed using injection imprecise voltage by using different voltages in a subtractive manner to be able to calibrate with respect to a voltage that is out of a desirable measurable range using measuring circuitry. Efficient background calibration of circuits is also achieved by providing an equivalent circuit element to circuit elements receiving an injected calibration signal, and switching circuit elements. Such imprecise voltages can be determined through such calibration, and then used to calibrate a second circuit generating the imprecise voltages.

FIELD OF THE INVENTION

The present invention relates to calibration of circuits, such asanalog-to-digital converters and precision resistor based circuits.

BACKGROUND OF THE INVENTION

In precision circuits where the values of resistors, capacitors,transistors, and other components whose values in actual circuitimplementations may be different from design specifications, eitherstatically or transiently due to environmental conditions such astemperature, calibration of such values is of paramount importance. Whena component value is calibrated and an error is detected, a physicalcomponent value can be changed or “trimmed” accordingly to compensatefor an error, or the circuit components can be left alone and the errorcorrected or compensated for either by built-in compensation circuitryor computation logic or by external compensation. In cases ofunacceptable errors or a lack of suitable compensation mechanism, thecircuit may need to be discarded.

Calibration may be performed in a variety of ways. Two general types canbe defined: background calibration; and foreground calibration. Inforeground calibration, operation of the circuit is stopped whilecalibration is carried out, while in background calibration, circuitoperation continues while calibration is carried out. Foregroundcalibration has the inherent advantage that test signals can be injectedinto the circuit without concern for the normal operation, and thedesired values to be calibrated can be measured as a function of testsignals. Measurement of the output values of the circuit as a whole orfrom selected circuit components or subcircuits is typically performedby additional testing logic, whether built-in or off-circuit. In thecase of an ADC for example, a test analog signal can be swept though thedynamic range of the ADC, and the digital output response can becompared. Additionally or alternatively, key components can be fedspecific test signals, and responses measured. Such test signals andresponse measurement are normally done by dedicated circuitry notinvolved in the normal operation of the circuit. In the case ofcalibrating a device, such as an analog-to-digital converter (ADC),there is significant advantage to being able to maintain precision ofthe device through background calibration without removing the devicefrom normal continuous use. However, it is inherently more challengingto measure circuit values without disrupting normal operation by the useof known rest signals.

In some types of precision circuit devices, such as pipelined ADC's, thedevices comprise interconnected stages, such as first stage precisioncircuitry whose output is measured by second stage precision circuitry.In the case of pipelined ADC's, the first stage converts one or moremost-significant bits (MSB) of the analog signal, generates from thosebits an analog signal to be subtracted from the input analog signal, andthe difference is amplified and measured in the next stage. The nextstage measures the next lesser significant bits, and the number ofstages may be two, three or more. The last stage is often essentially aflash ADC. Flash ADC devices gain complexity and consume power almostgeometrically for each additional bit of resolution added. PipelinedADC's allow greater resolution without geometrically increasingcomplexity and power consumption, with the trade-off that each stagebeyond the first introduces a sample delay in the output of the ADC.

SUMMARY OF THE INVENTION

It has been discovered that efficient calibration of circuits can beperformed using imprecise voltages by using different voltages in asubtractive manner to be able to calibrate with respect to a voltagethat is out of a desirable measurable range using measuring circuitry.The resulting calibration becomes independent of the exact value of theimprecise voltages. It has been further discovered that such imprecisevoltages can be determined through such calibration, and then used tocalibrate a second circuit generating the imprecise voltages.

It has been discovered that efficient background calibration of circuitscan be performed by providing an equivalent circuit element to circuitelements receiving a calibration signal, and switching circuit elements.

According to one aspect of the invention, a digital backgroundcalibration technique to compensate for the nonlinearity and gain errorin the sub-digital-to-analog converter (SDAC), amplifier finite DC gain,and reference voltage inaccuracy in multi-bit/stage pipelinedanalog-to-digital converter (ADC) is provided. By injecting subtractiveimprecise voltages (SIV) in a modified conventional multi-bitmultiplying digital-to-analog converter (MDAC) and performingcorrelation based successive coefficient measurements (SCM), abackground calibration is achieved. This calibration does not needaccurate calibration voltages or increasing the SDAC resolution.

Further, a global gain correction (GGC) for time-interleaved ADCs isprovided. Techniques to shorten the calibration duration are furtherprovided. Simulation results demonstrate that in the presence ofrealistic capacitor and resistance mismatch and finite op-amp gain,these techniques improve the linearity by several bits in single andmulti-channel pipelined ADC.

According to one aspect of the invention, there is provided a method ofbackground calibrating a circuit to be calibrated having a plurality ofcircuit elements and providing an output residue. The method comprisesswitching one of the circuit elements to be substituted by an equivalentcircuit element within the circuit, and injecting at least onecalibration signal into at least one of the circuit elements, whereinthe calibration signal causes a measurable change in the output residue.The measurable change is measured and a calibration parameter for thecircuit is calculated based on the change, and a calibration correctionto an output of the circuit is performed using the parameter.Optionally, the calibration correction comprises correcting for themeasurable change.

In the case that the output residue is essentially an AC signal, thechange may be measured by obtaining an average of the output residuewith the calibration signal injected and an average of the outputresidue without the calibration signal injected, the change being adifference between the averages. In this case, the injecting maycomprise alternating between no injecting and injecting of thecalibration signal from measurement to measurement. So that the averagesmay be free of aliasing, the injecting may alternate in a random orpseudorandom manner.

In some embodiments, the circuit is a pipelined ADC comprising aplurality of stages, the measuring being performed using the stagesdownstream of one of the stages whose circuit elements are beingcalibrated, the magnitude of the measurable change being small enoughsuch that the output residue is within a dynamic range of the downstreamstages.

According to another aspect of the invention, there is provided a methodof calibrating a voltage reference. The method comprises providing afirst circuit having a plurality of calibrated circuit elements andgenerating an output residue having a dynamic range for measurement, thecalibrated circuit elements having a known value. At least twocalibration signals are provided to operate in the first circuit in asubtractive manner so that the output residue remains within the dynamicrange. This involves providing a group of different imprecise voltagesfor the calibration signals having at least one value that used alonewould cause the residue to lie outside the dynamic range and at leastone value that used alone would cause the residue to lie within thedynamic range, selecting a series of different combinations of ones ofthe group of imprecise voltages for injection in the subtractive manner,the series of combinations including one of the imprecise voltages to beisolated once, a remainder of the imprecise voltages each used in two ofthe different combinations, with one of the different combinationscomprising a zero voltage and one of the imprecise voltages having avalue that used alone would cause the residue to lie within the dynamicrange, and injecting in the first circuit each of the differentcombinations of the imprecise voltages as the calibration signals. Themeasurable change for each of the different combinations is measured,and from a sum of the change measured for each of the differentcombinations, a value is calculated that is a function of the one of theimprecise voltages to be isolated independently of the remainder of theimprecise voltages. Preferably, the first circuit may comprise circuitrythat outputs as the residue a difference between the calibrationsignals, the reference value being the value calculated that is equal tothe one of the imprecise voltages to be isolated.

In a preferred embodiment, the group of imprecise voltages comprises astring resistance connected at one end to a reference voltage and to thezero voltage at another end. In this case, steps of the method can berepeated to identify a ratio of resistances in the string resistance.

According to another aspect of the invention, there is provided amultiplying-digital-to-analog (MDAC) circuit for use in a backgroundcalibrated pipelined analog-to-digital (ADC) circuit. The MDAC comprisesa plurality, n, of inputs from a sub-digital-to-analog converter (SDAC),an amplifier, a feedback capacitor and switches for connecting thefeedback capacitor in a first state between ground and a first modulatedvoltage, and in a second state between an input of the amplifier and anoutput of the amplifier, a switch matrix having a plurality, n+1, ofoutputs for controllably directing, in response to a control signal, theinputs from the SDAC and a second modulated voltage, and a plurality,n+1, of summing capacitors connected on one side to the input of theamplifier and connected on another side, in the first state, viaswitches to a stage input voltage and, in the second state, via switchesto an output of a corresponding one of the switch matrix outputs.Preferably, the switch matrix comprises a plurality, n+1, ofmultiplexers, wherein n of the multiplexers have one input connected toa corresponding one of the inputs from the SDAC, and an (n+1)th one ofthe multiplexers has an input from each of the inputs from the SDAC, themultiplexers each having an input from the second modulated voltage, andproviding a corresponding one of the switch matrix outputs.

According to a further aspect of the invention, there is provided amethod of background calibrating a pipelined ADC circuit to becalibrated having a plurality of circuit elements and providing anoutput residue. The method comprises injecting at least one calibrationsignal into at least one of the circuit elements of a stage of the ADCunder calibration, wherein the calibration signal causes a measurablechange in the output residue of the stage, predicting a value of theoutput residue of the stage without the injecting, using a backend ADCof the pipelined ADC to measure an output residue of a stage upstream ofthe stage under calibration, and predicting a value of a sub-DAC outputof the stage under calibration, measuring the change using the outputresidue of the stage under calibration using the backend ADC, thepredicted value of the output residue of the stage without theinjecting, and the predicted value of the sub-DAC output of the stageunder calibration, calculating a calibration parameter for the circuitbased on the change, and performing a calibration correction to anoutput of the circuit using the parameter. Preferably, the measuring ofthe change may comprise obtaining an average of the comparison of theoutput residue with the predicted value.

According to a further aspect of the invention, there is provided amethod of background calibrating a circuit to be calibrated having aplurality of circuit elements and providing an output residue in whichthe residue occupying an identified frequency range during normaloperation. The method comprises injecting at least one calibrationsignal into at least one of the circuit elements of the circuit, whereinthe calibration signal causes a measurable change in the output residueof the stage, and alternating between no injecting and injecting of thecalibration signal from measurement to measurement at an injectionfrequency resulting in the measurable change having a frequency outsideof the frequency range. The method then comprises detecting theidentified frequency range, and setting the injection frequency suchthat the measurable change has a frequency outside the identifiedfrequency range, filtering the residue to detect the change at thefrequency outside of the frequency range, calculating a calibrationparameter for the circuit based on the change, and performing acalibration correction to an output of the circuit using the parameter.In some embodiments, when there is no suitable injection frequencyresulting in the measurable change having a frequency outside of thefrequency range, then the change may be measured by obtaining an averageof the output residue with the calibration signal injected and anaverage of the output residue without the calibration signal injected,the change being a difference between the averages, the injectingalternating in a random or pseudorandom manner, whereby the averages arefree of aliasing. In the case that the circuit is a pipelined ADCcircuit, the step of filtering may comprise using a backend ADC of thepipelined ADC to measure the filtered residue.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be better understood by way of the following detaileddescription of a preferred embodiment with reference to the appendeddrawings, in which:

FIG. 1 is a block diagram of a multi-bit/stage pipelined ADC accordingto the prior art;

FIG. 2 is a circuit diagram of a 2.5 bit per stage multiplyingdigital-to-analog converter (MDAC) according to the prior art;

FIG. 3A is a plot of the residue of a realistic 2.5 bit per stage MDACcompared to an ideal one;

FIG. 3B is a similar plot of the residue of a realistic 2.5 bit perstage MDAC illustrating the change in the residue as a result ofinjecting a calibration signal;

FIG. 4 is a plot of the input-output relationship of the overallpipelined ADC comparing ideal, uncalibrated and calibrated responses;

FIG. 5 is a block diagram showing digital calibration logic used in thefinal digital output construction in a pipelined multi-bit per stageADC;

FIG. 6 is a plot illustrating the transfer functional of 2 ADC'scompared with an ideal one;

FIG. 7 is a block diagram of a modified 2.5 bit per stage multiplyingdigital-to-analog converter (MDAC) according to the preferred embodimentin which the modified MDAC is used for background calibration of amultibit per stage pipelined ADC digital calibration;

FIG. 8A is a block diagram of a simplified example wherein thesubtractive imprecise voltage (SIV) background calibration technique isapplied to the first stage of a pipelined ADC;

FIG. 8B is a block diagram of a multi-bit/stage pipelined ADC includingbackground calibration according to the preferred embodiment;

FIG. 8C is a block diagram identical to FIG. 8B with the addition thatthe imprecise voltage source being shared with a precise-resistive basedapplication circuit;

FIG. 9 is a block diagram of a switching matrix used to generatecalibration voltages V₁ and V₂ from a string resistance dividing thevoltage (+V_(R))−(−V_(R));

FIG. 10 illustrates a filter characteristic of a filter used to measureinjected calibration signals in a residual output, the residual outputhaving a maximum frequency during normal operation less than fs/2, andthe injected signal being injected at a frequency of fs/2;

FIG. 11 is a block diagram of an embodiment of a background calibratedpipelined ADC in which the backend stage operates at double frequency tobe able to measure the residual of two stages;

FIG. 12 is a block diagram of an embodiment of a background calibratedpipelined time-interleaved ADC;

FIG. 13 shows a matrix used to generate the voltages V₁ and V₂ when K=4;

FIG. 14 is a circuit diagram of a resistor string DAC;

FIG. 15 is a circuit diagram of an R/2R DAC;

FIG. 16 is a circuit diagram of an op-amp/filter having control switchesfor configuration between calibration and normal operation phases;

FIG. 17 is a circuit diagram of a charge capacitive DAC;

FIG. 18 is a circuit diagram of a trimmed analog circuit using afeedback voltage;

FIG. 19 is a circuit diagram of a prior art sample-and-hold circuit;

FIG. 20 is a circuit diagram of a modified sample-and-hold circuitaccording to an embodiment of the invention; and

FIGS. 21 a, 21 b and 21 c illustrate the transfer function of thesample-and-hold circuit according to the embodiment of FIG. 20.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

According to the preferred embodiment, a novel digital backgroundcalibration technique that corrects for the nonlinearity and gain errorin the sub-DAC (SDAC), amplifier finite DC gain and reference voltageinaccuracy in a multi-bit/stage pipelined ADC is provided. Thisbackground calibration technique does not rely on accurate injectedcalibration voltages that are difficult to be obtained on chip or thatwould increase the SDAC or SADC precision or even split up the capacitorsizes that limit the maximal achievable speed. Also a global gaincorrection (GCC) useful for time-interleaved ADC (TIADC) and techniquesto shorten the calibration duration are provided.

Multibit/Stage Pipelined ADC Digital Calibration

The general block diagram of a pipelined ADC where front-end stagesresolve several bits (e.g 2.3 or 3.5) is shown in FIG. 1. The outputresidue V_(n) of stage i is expressed as:V _(n) =G ₁·(V ₁ −V _(z,999) )   (1)Where V_(z,999) and G₁ are the SDAC analog output and the interstagegain respectively.

The input of the entire pipelined ADC can be obtained by:$\begin{matrix}{V_{in} = {V_{{dac}\quad 1} + \frac{V_{{dac}\quad 2}}{G_{1}} + \frac{V_{{dac}\quad 3}}{G_{1}G_{2}} + \ldots + \frac{V_{dacp}}{G_{1}G_{2}\ldots\quad G_{p - 1}} + \Delta}} & (2)\end{matrix}$where Δ stands for the quantization error of the entire ADC.

According to Eq. (2) the input signal can be accurately generated whenthe effective values of V_(z,999) and G₁ are used. Capacitor mismatchcreates non-linearity in the SDAC that limits the precision of V_(z,999). Also the capacitor mismatch and the finite opamp gain deviate G₁ fromits ideal value.

The MDAC circuit of FIG. 2 includes the SDAC, the adder and theamplifier illustrated in the schematic expansion of the Stage 2 block ofFIG. 1. On φ₁, the analog voltage from the sample and hold circuit, SHA,is loaded onto the capacitors, while on φ₂, the amplifier feedbackthrough C₁—is connected, and the digital values from the sub-ADC (SDAC)are loaded on the capacitors to measure the difference between V_(i) andV_(DAC). For a 2.5 bit/stage multiplying digital-to-analog converter(MDAC), as shown in FIG. 2, the residue voltage can be derived as:$\begin{matrix}{V_{p} = {{{G_{A} \cdot G_{p} \cdot \text{(}}V_{1}} - V_{{dac}\quad 1} + {{\frac{C_{T} + C_{p}}{C_{t}} \cdot V_{as}}{where}}}} & (3) \\{C_{T} = {C_{f} + C_{1} + C_{2} + C_{3}}} & (4) \\{G_{A} = {1/\left( {1 + {1/{Af}}} \right)}} & (5)\end{matrix}$

and G_(A) is the interstage gain due to the finite opamp gain A that isideally equal 1.

The feedback factor f is equal:f=C _(f)/(C _(T) +C _(P))   (6)

C_(P) is the virtual ground parasitic capacitance.G _(C)=(C ₁ +C ₂ +C ₃ +C _(i))/C _(f)   (7)

G_(C) is the interstage gain due to SDAC ideally equal 2².G ₁ =G _(A) ·G _(C)   (8)V _(z,999) =(d ₁ ·C ₁ +d ₂ ·C ₂ +d ₃ ·C ₃)·V _(R) /C _(T)   (9)

G₁ is the interstage gain and V_(z,999) is the SDAC output.

V_(R) is the reference voltage and d₁ are the digital output code of theSADC where d₁∈{−1,0,1 } and d=Σ_(z,999) ³d_(i).

FIG. 3A depicts the residue plot of a realistic 2.5 bit/stage given byEq. (3) compared with an ideal one. Nonlinearity of the SDAC and theinter-stage gain error, due to the deviation of G₁ from 2², introducemismatch in the residue jumps in the different boundaries of the digitalcode d. FIG. 3A shows the effect of this error on the input-outputrelationship of the overall pipelined ADC when the stage i is consideredas the first stage and the remaining stages were ideal. Thediscontinuities, generally referred to as major-carry jumps in theuncalibrated ADC curve shown in FIG. 3A, cause deleterious missing codesand harmonic distortion that degrade considerably the ADC performance.

By measuring exactly the value of the jumps G_(A)·(C_(i)/C_(f))·V_(n) inthe residue and by using the following equation, the residue outputbecomes linear when it is referred to the input of the stage i despitethe gain errors of the SDAC and the opamp, and the reference voltageinaccuracy. $\begin{matrix}{{V_{o} - {\sum\limits_{l = 1}^{3}{d_{1} \cdot G_{A} \cdot \frac{C_{i}}{C_{f}} \cdot V_{R}}}} = {G_{A} \cdot G_{C} \cdot V_{i}}} & (10)\end{matrix}$

Ideally the gain is equal to 2^(n−1) for n-bit SADC in the stage i.After the correction using Eq. (10) the backend, constituted now fromthe stage i and the following stage, is linear with a global gainG_(i)−G_(A)·G_(C).

When the stage i is the first stage and after calibrating the ADC thecalibrated transfer curve is shown in FIG. 4, where the input-outputrelationship is linearized and the global gain is equal to the idealgain multiplied by G₁/2^(n−1). After measuring the errors associatedwith stage i, stage i−1 can be calibrated using the linearized backendformed from stage i and its following stages.

The final digital output D_(out) is constructed, as shown in FIG. 5, bystarting the correction from the least significant stages to the mostsignificant ones.

Global Gain Correction

Several calibration methods cause the slope of the overall ADC transfercharacteristic to depend on the actual residue gains and is thereforenot well controlled. FIG. 4 shows that the final gain is multiplied byG_(i)/2^(n−1) in the case of correction of the first stage. The globalgain mismatch is harmful for some applications such as time interleavedADC (TIADC) that are inevitable when increasing the speed is desiredwith high resolution ADCs to overcome the technology limits. With gainmismatch between the different channels, inband distortions are createdand that degrades considerably performance of time-interleaved ADCsystems, as for example is known from the article by N. Kurosawa, H.Kobayashi, K. Maruyama, H. Sugawara and K. Kobayashi, titled “Explicitanalysis of channel mismatch effects in time-interleaved ADC systems,”and published in IEEE Trans. Circuits Syst. I, vol. 48, pp. 261-271,March 2001. In FIG. 6, the transfer functions of 2 ADCs are comparedwith an ideal one. By succeeding in measuring the global gainG_(i)/2^(n−1), and G₂/2⁻²for the channels ADC₁ and ADC₂, a global gaincorrection is possible by dividing the final digital output of each ADCby 2^(n−1)/G₁ and 2^(n−1)/G₂ respectively (FIG. 6).

In the case of calibrating the first stages in ADC₁ and ADC₂, the gainG₁ (i=1,2) can be computed using the following equation, $\begin{matrix}\begin{matrix}{G_{1} = {G_{A} \cdot G_{C}}} \\{= {\left( \frac{C_{f} + C_{1} + C_{2} + C_{3}}{C_{f}} \right) \cdot G_{A}}} \\{= {G_{A} + {G_{A} \cdot \frac{C_{1}}{C_{f}}} + {G_{A} \cdot \frac{C_{2}}{C_{f}}} + {G_{A} \cdot \frac{C_{3}}{C_{f}}}}}\end{matrix} & (11)\end{matrix}$

This equation indicates that for a global gain correction (GGC), aseparate measurement for the gain G_(A) from the other products inEq.(10) needs to be performed.

Digital Background Calibration

In the background calibration method of the preferred embodiment, theteam G_(A)(C_(i)/C_(f))V_(R) is measured for the different values ofC_(i) to enable the usage of Eq. (10). A schematic of a modified 2.5-bitMDAC according to the preferred embodiment is shown in FIG. 7. The mostsignificant modification of this MDAC from the conventional one is theaddition of an extra capacitor C₄. Furthermore, voltage V₁·P_(N) issampled onto the feedback capacitor C_(f) when φ₁ is high, where P_(N)is a pseudorandom signal alternating between 0 and 1. FIG. 3Billustrates the influence of P_(N) on the MDAC response.

Capacitor C₄ is used instead of C_(f) to sample the input voltage whenφ₁, is high. By doing so, a voltage equal G_(A)·V₁ is injected in theresidue output. In background calibration, V_(in) is an unknown, andthus an average of the residue is calculated. With reference to theresidue plot of FIG. 3, it will be appreciated that the residue averageacross all d_(i) values has a “DC” mean value, the latter beingincreased when P_(N) is 1 by ΔV=G_(A)·(V₁−(C₄/C_(f))V₃) and thenreturning its normal value when P_(N) is 0. When the averaging iscomplete for C₄, and ΔV is measured, the multiplexers in FIG. 7 arecontrolled to calibrate the next in the remainder of the capacitors.

To not consume much from the offset correctable range of the SADC, V₁should be a small and stable analog voltage. A voltage could be injectedby splitting up the unit capacitor but the voltage V₁ cannot be madearbitrarily small. Also, splitting up the capacitors will limit themaximal achievable speed because, in this case, sampling capacitorsbigger than the minimal possible size will be used. For this reason, avoltage V₂−P_(N) is sampled onto the capacitor C₄ in the next phase whenφz,999 is high. The voltage V₁ and V₂ do not need to be accurate (asexplained below). By injecting these voltages, a subtractive imprecisevoltage (SIV) is injected in output residue for the stage undercalibration given by: $\begin{matrix}{V_{o} = {{G_{A} \cdot \left( {{G_{C} \cdot V_{1}} - {\frac{{d_{1} \cdot C_{1}} + {d_{2} \cdot C_{2}} + {d_{3} \cdot C_{3}}}{C_{f}} \cdot V_{R}} + {P_{N} \cdot V_{1}} - {P_{N} \cdot \frac{C_{2}}{C_{f}} \cdot V_{2}} + {\frac{{\sum\limits_{t = 1}^{N}C_{1}} + C_{f} + C_{P}}{C_{f}} \cdot V_{o\quad 3}}} \right)} = {{G_{A} \cdot \left( {V_{1} - {V_{2} \cdot \frac{C_{o}}{C_{f}}}} \right) \cdot P_{N}} + V_{o\quad 1}}}} & (12)\end{matrix}$where G_(C)=(C₁+C₂+C₃+C₄)/C_(f) and V_(z,999) is the remaining term inV_(n).

A simplified example wherein the SIV technique is applied to the firststage is shown in FIG. 8A. By correlating the backend ADC digital outputD[V_(n)] with P_(N) the term ΔV=G_(A)·(V₁−(C₄/C_(f))V₂) is extracted.P_(N1) is used for correlation instead of P_(N), Where P_(N1)alternatesbetween −1 and +1 instead of 0 and 1 in P_(N). That substitutionaverages out the mean of the remaining term D[V_(n1)] since P_(N1) has amean value of 0.

The output of the averager Δe is given by: $\begin{matrix}\begin{matrix}{{\Delta\quad e} = {\frac{1}{N}{\sum\limits_{k = 1}^{N}\left( {{D\left\lbrack {V_{o}(k)} \right\rbrack} \cdot {P_{N\quad 1}(k)}} \right)}}} \\{= {{\frac{1}{N}{\sum\limits_{k = 1}^{N}\left( {{D\left\lbrack {\Delta\quad V} \right\rbrack} \cdot {P_{N}(k)} \cdot {P_{N\quad 1}(k)}} \right)}} +}} \\{\frac{1}{N}{\sum\limits_{k = 1}^{N}\left( {{D\left\lbrack {V_{o\quad 1}(k)} \right\rbrack} \cdot {P_{N\quad 1}(k)}} \right)}}\end{matrix} & (13)\end{matrix}$

The expected value of Δe is: $\begin{matrix}\begin{matrix}{{E\left\lbrack {\Delta\quad e} \right\rbrack} = {{\frac{D\left\lbrack {\Delta\quad V} \right\rbrack}{N}{\sum\limits_{k = 1}^{N}\left( {{E\left\lbrack {{P_{N}(k)} \cdot {P_{N\quad 1}(k)}} \right\rbrack} \cdot} \right)}} +}} \\{\frac{1}{N}{\sum\limits_{k = 1}^{N}{E\left\lbrack {{D\left\lbrack {V_{o\quad 1}(k)} \right\rbrack} \cdot {P_{N\quad 1}(k)}} \right\rbrack}}} \\{= {\frac{1}{2} \cdot {D\left\lbrack {\Delta\quad V} \right\rbrack}}}\end{matrix} & (14)\end{matrix}$

Since D[V_(o1)] and P_(N1) are uncorrelated and E[P_(N)(k)·P_(N1)(k)]=½,the variance, σ_(z,999) ², of Δe is: $\begin{matrix}\begin{matrix}{\sigma_{\Delta\quad\sigma}^{2} = {{E\left\lbrack {\Delta\quad e^{2}} \right\rbrack} - {E\left\lbrack {\Delta\quad e} \right\rbrack}^{3}}} \\{= {\frac{1}{N^{2}}{\sum\limits_{t = 1}^{N}\left( {{E\left\lbrack {D\left\lbrack {V_{n\quad 1}(k)} \right\rbrack}^{2} \right\rbrack} \cdot {E\left\lbrack {P_{N\quad 1}^{2}(k)} \right\rbrack}} \right)}}} \\{= {\frac{1}{N}\sigma_{D{\lbrack V_{o\quad 1}\rbrack}}^{2}}}\end{matrix} & (15)\end{matrix}$where σ_(VN1) ²=E[P_(N1) ²(k)]=1.

The averager output is not constant in the steady state. Instead, itcontains a random fluctuation caused by the term involving the varianceof D[V_(n1)]. Because this term is accumulated, however, it can be madearbitrarily small by increasing the number of samples (N) at the inputof the averager in FIG. 8A.

In the simplified example of FIG. 8A, only the first stage iscalibrated. It will be appreciated that the modified MDAC of FIG. 7 isused to perform calibration for each term related to each capacitor inorder to achieve full calibration. In the complete block diagram of FIG.8B illustrating the preferred embodiment, two stages 20 a and 20 b arecalibrated, and the calibration control system 50 is shown. Thepseudorandom generator 54 provides two uncorrelated streams of binarysignals, P_(N1) and P_(N2). As in FIG. 8A, the signals may be convertedfrom a 0 and 1 state used in the FIG. 7 into a −1 and +1 state for usein correlation so that the mean correlation has a value of 0. Theimprecise voltages V₁ and V₂ used in MDAC 24 a and V₃ and V₄ used inMDAC 24 b are provided by a voltage switching matrix 52. The controlunit 50 outputs control signals for the switching matrix 52 and themuxes of the MDAC's 24 to select a capacitor to receive the imprecisevoltage selected. The controls signals are also communicated to thesuccessive coefficient measurement unit 46 that analyses the averagederrors Δe₁ and Δe₂ to determine the correction values associated witheach capacitor in the MDAC's. The ADC calibration logic 40 uses thecorrection values from unit 46 along with the random values P_(N1) andP_(N2) to process each sample from the ADC uncorrected output from thedigital error correction unit 30 to provide the desired corrected outputsamples. Global gain correction, that is particularly desirable in thecontext of a time-interleaved ADC, is schematically illustrated as beingperformed in unit 48 on the output of calibration logic 40. Of course,global gain correction can be performed within logic 40.

The voltages injected into MDAC 24 b cause a measurable change in theresidual V_(o2) that is measured by the backend ADC 20 c. The residueV_(o1) is measured by the sub-ADC of stage 20 b. Measurement of themeasurable change caused by the subtractive injection is done using acorrelator 44 a,44 b and averaging unit 42 a,42 b for the respectivestages under calibration to provide the respective averaged errors Δe₁and Δe₂.

Increasing the number of samples N to achieve calibration meansincreasing the required calibration time. In the following, twotechniques to accelerate the convergence rate at a low overhead aredescribed. In the preferred embodiment, the term G_(A)(C₄/C_(f))V_(R) isfound by injecting subtractive imprecise voltages (SIV) and performingsuccessive coefficient measurements (SCM) as explained below. In thefirst coefficient measurement, V₁ is set equal to (K−1)V_(R)/K and V₃equal to V_(k) where K is an even number. In that case, a term g₁ ismeasured. In the second one V₁ is set to (K−1)V_(R)/K, V₂ equal to(K−2)V_(R)/K and coefficient g₁ is obtained. At the K−1 measurement V₁is set to V_(R)/K, V₂ to 2·V_(n)/K, and it gives g_(R−1). Finally V₁ isset to V_(R)/K and V₃ to ground and g_(k) is obtained.

Using the following equations:g ₁ =G _(A)·(((K−1)·V _(R) /K)−(C ₄ /C _(f))·V _(R) /K)g ₁ =G _(A)·(((K−1)·V _(R) /K)−(C ₄ /C _(f))·((K−2)·V _(R) /K)))g ₃ =G _(A)·((K−3)·(V _(R) /K)−(C ₄ /C _(f))·((K−2)·(V _(R) /K)))g ₄ =G _(A)·((K−3)·(V _(R) /K)−(C ₄ /C _(f))·((K−4)·(V _(R) /K)))g _(K−2) =G _(A)·((3·V _(R) /K)−(C ₄ /C _(f))·(2·V _(R) /K))g _(K−1) =G _(A)·((V _(R) /K)−(C ₄ /C _(f))·(2·V _(R) /K))g _(K) =G _(A)·(V _(R) /K)   (16)the term G_(A)(C₄/C_(f))V_(n) is obtained by:G _(A)(C ₄ /C _(f))V _(n) =−g ₁ +g ₂ −g ₃ +g ₄ − . . . +g _(K−2) −g_(K−1) +g _(K)   (17)

The same procedure is repeated for every capacitors where C₄ willreplace the one used in the coefficient measurement procedure.

The reference voltages used in SGM do not need to be accurate becausethere are eliminated from Eq. (17) and a simple string resistance can beused to measure the gain term. The same string resistance used togenerate the references of the SADC could be used.

If K is chosen to be equal 8, in every coefficient measurement a voltagearound V_(R)/8 is injected in the second stage. Injecting such smallvoltage means that the non-overload range equal V_(R)/2−V_(R)/8 is leftfor SADC correction. That non-overload range can correct SADC offset upto =(¾)V_(R)/8 instead of =V_(R)/8 in 2.5 b/stage without this method.This will alleviate the comparator requirements compared to othercalibration methods where a precise voltage of V_(R)/4 is injectedleaving non-overload range of V_(R)/4 and offset correctable range of±(½)V_(R)/8 (see E. Siragusa and I. Galton, “A digitally enhanced 1.8V15 b 50 MS/s CMOS pipelined ADC,” ISSCC Dig. Tech. Papers, pp. 452-453,February 2004). Moreover ilte comparator offset correctable range canincrease arbitrarily to approach ±V_(R)/8 by using more referencevoltages and by performing more SGM.

Setting K equal to 8 means 8 calibration cycles are needed to measureevery coefficient G_(A)(C_(i)/C_(f))V_(R). The addition of the 8coefficients means that the variance in eq. (15) is now 8 times higher.To obtain the same resolution for the gain as one coefficientmeasurement, the number of samples in every measurement needs to be 8·Ninstead of N. Knowing that we need 8 gain measurements so the totalnumber of samples needed is 8·(8·N). To shorten the gain calibration toonly one cycle of measurement (e.g. 8·N) the calibration voltages areapplied in the following manner. In the first sample V₁ is set equal to(K−1)V_(R)/K and V₂ equal to V_(N) so the injected coefficient is equalto g₁. In the second sample, we set V₁ and V₃ to obtain g₁ and so onuntil injecting the voltage that gives the coefficients g_(z,999) .After g_(z,999) , the injected voltages are repeated to obtain g₁ againand so on. In this case the averager output is written as:$\begin{matrix}\begin{matrix}{{\Delta\quad e} = {\frac{1}{N}{\sum\limits_{k = 1}^{N}\left( {{D\left\lbrack {V_{o}(k)} \right\rbrack} \cdot {P_{N\quad 1}(k)}} \right)}}} \\{= {{\frac{1}{N}{\sum\limits_{k = 1}^{N}\left( {{D\left\lbrack g_{1} \right\rbrack} \cdot {P_{{Ns}\quad 1}(k)} \cdot {P_{N\quad 1}(k)}} \right)}} + \ldots +}} \\{{\frac{1}{N}{\sum\limits_{k = 1}^{N}\left( {{D\left\lbrack g_{8} \right\rbrack} \cdot {P_{{Ns}\quad 8}(k)} \cdot {P_{N\quad 1}(k)}} \right)}} +} \\{\frac{1}{N}{\sum\limits_{k = 1}^{N}\left( {{D\left\lbrack {V_{o\quad 1}(k)} \right\rbrack} \cdot {P_{N\quad 1}(k)}} \right)}}\end{matrix} & (18) \\\begin{matrix}{{8 \cdot {E\left\lbrack {\Delta\quad e} \right\rbrack}} = {{\frac{1}{2} \cdot \left( {{{D\left\lbrack g_{1} \right\rbrack}\cdots} + {D\left\lbrack g_{A} \right\rbrack}} \right)} +}} \\{\frac{1}{N}{\sum\limits_{k = 1}^{N}{E\left\lbrack {{D\left\lbrack {V_{o\quad 1}(k)} \right\rbrack} \cdot {P_{N\quad 1}(k)}} \right\rbrack}}} \\{= {\frac{1}{2} \cdot {D\left\lbrack {{G_{A}\left( {C_{t}/C_{f}} \right)}V_{R}} \right\rbrack}}}\end{matrix} & (19) \\\begin{matrix}{{{where}\quad{E\left\lbrack {{P_{Nu}(k)} \cdot {P_{N\quad 1}(k)}} \right\rbrack}} = {\frac{1}{16}\quad{and}\quad{the}\quad{variance}\quad{of}}} \\{{\Delta\quad e_{1}} = {{8 \cdot \Delta}\quad e\quad{is}\text{:}\quad\sigma_{\Delta\quad e_{1}}^{2}}} \\{\frac{8}{N^{2}}{\sum\limits_{t = 1}^{N}\left( {{E\left\lbrack {D\left\lbrack {V_{o\quad 1}(k)} \right\rbrack}^{2} \right\rbrack} \cdot} \right.}} \\\left. {E\left\lbrack {P_{N\quad 1}^{2}(k)} \right\rbrack} \right) \\{= {\frac{8}{N}\sigma_{D{\lbrack V_{o\quad 1}\rbrack}}^{2}}}\end{matrix} & (20)\end{matrix}$

So to obtain the same resolution as the one coefficient (e.g. g₁)measurement N should be multiplied by 2³ and only one measurement issufficient to determine G₄(C_(i)/C_(f))V_(R). It will be appreciatedthat the gain measurement does not need the injection of an accurateanalog voltage or an increasing in the SDAC linearity or even splittingup the minimal size capacitor that limit the speed.

By using the capacitor C₄ instead of C_(f) to sample the input voltagewhen φ₁ is high in the modified MDAC, the interstage gain G_(A)·G_(C) isnow constant despite periodically changing of the capacitor undermeasurement. Also this modification avoids the need to measure G_(A) andG_(A)(C_(i)/C_(f)) separately as indicated in eq. (11). In thisembodiment, the term given in eq. (11) is constructed for the modifiedMDAC of FIG. 7 in the digital domain by summing the already measuredterms G_(A)(C_(i)/C_(f)) related to every capacitor: $\begin{matrix}\begin{matrix}{{D\left\lbrack G_{1} \right\rbrack} = {D\left\lbrack {\left( {\left( {C_{1} + C_{2} + C_{3} + C_{4}} \right)/C_{f}} \right) \cdot G_{A}} \right\rbrack}} \\{= {{D\left\lbrack {G_{A} \cdot \left( {C_{1}/C_{f}} \right)} \right\rbrack} + {D\left\lbrack {G_{A} \cdot \left( {C_{2}/C_{f}} \right)} \right\rbrack} +}} \\{{D\left\lbrack {G_{A} \cdot \left( {C_{3}/C_{f}} \right)} \right\rbrack} + {D\left\lbrack {G_{A} \cdot \left( {C_{4}/C_{f}} \right)} \right\rbrack}}\end{matrix} & (21)\end{matrix}$and then the corrected digital output of the ADC is divided by G₁. Inthe case of several stages to be corrected, G_(A) given in eq. (21) willbe measured directly multiplied by the new gain of the backend ADC(G_(z,999) ) where G_(A)=G_(z,999) ·(1/(1+1/Af)). And then, G₁ isconstructed by the same equation given in eq. (21).Calibration Duration Shortening

Two techniques that shorten the calibration duration are provided Eq.(15) indicates that the calibration cycles can be shortened byincreasing N or by reducing the variance of D[Vol]. The first techniqueis applicable when an anti-aliasing filter precedes the ADC (e.g. theADC is not used for under-sampling) and that only the first stage of theADC needs to be calibrated. In this case, this filter could be made toprovide a 0 power at the frequency f_(z,999) /2. In this case, P_(N)could be alternate between +1 and 0 periodically to modulate thecalibration term at f_(z,999) /2 as shown in FIG. 10. That willeliminate the interference between the calibration term and thefull-scale spread input signal and that will reduce the number ofsamples needed.

It will be appreciated that The residue or residual voltage D[Vol]occupies an identified frequency range during normal operation. Theinjecting of the calibration signal involves alternating between noinjecting and injecting of the calibration signal from measurement tomeasurement at a frequency resulting in the measurable change in D[Vol]having a frequency outside of the identified frequency range. Themeasuring of the change uses filtering of the residue D[Vol] to detectthe change at the frequency outside of said frequency range. This givesthe value of the change in D[Vol] without long averaging. Since thefrequency range of the ADC input can occupy any or all of the range ofthe ADC, the frequency range can be detected during operation. It canthen be determined whether there is a suitable frequency resulting inthe measurable change having a frequency outside of the frequency rangeof D[Vol]. If there is such a suitable frequency then a filter isadvantageously to obtain the measure of the change more quickly. If not,then the change is measured by obtaining an average of the outputresidue with the calibration signal injected and an average of theoutput residue without the calibration signal injected. The change isthen a difference between the two averages, and the injecting is done ina random or pseudorandom manner, so that the averages are free ofaliasing.

When the ADC has no empty spectrum to modulate the calibration signal onit, the input signal will be spread all over the bandwidth whenmultiplied by a pseudo-random P_(N) sequence. Knowing that the inputsignal is preferred to be full-scale to maximize the dynamic range, theinput variance can be decreased by subtracting Vol from eq. (15). Tocalibrate a multibit per stage pipelined ADC, the input to be subtractedis the input of the stage under calibration and not necessarily theinput signal (except for the first stage). Usually a multibit per stagepipetined ADC has front-end stages resolving several bits (e.g 2.3 or3.5) and a backend constituted from 1.5 b/stages as shown in FIG. 1. Inthis embodiment, the backend ADC and the SADC for the stages undercalibration are used to predict the variance of Vol during the normaloperation of the ADC. Knowing that the accuracy required from thebackend ADC is relaxed and also knowing that the stages in the backendare configured as 1.5 b/stage, this backend can be run at double speedwithout the need for additional overhead (see FIG. 11).

When stage 2 is undergoing calibration in one cycle, the backend ADC isconnected to the input of stage 2 (Cal=1) to estimate the input signalV_(z,999) . In the next period, the backend ADC performs its normaloperation for the whole ADC. V_(z,999) is sampled at f_(z,999) while thebackend is operating at 2·f_(z,999) that means that this voltage isconstant during the 2 operations.

The value obtained by backend ADC during the normal operation of the ADCis:V _(z,999 2) =G ₂·(V _(z,999 1) −V _(DAC2))+ΔV·PN   (22)

If we subtract from V_(z,999) the value estimated by the backend{circumflex over (v)}_(z,999) multiplied by 2² instead of G₂ and byusing the output of SADC to estimate the SDAC output ({circumflex over(V)}_(z,999) ) multiplied by 2² Eq. (22) becomes: $\begin{matrix}\begin{matrix}{V_{{res}\quad 2{\_ new}} = {\left( {{G_{2} \cdot V_{{res}\quad 1}} - {2^{2} \cdot {\hat{V}}_{{res}\quad 1}}} \right) +}} \\{\left( {{G_{2} \cdot V_{{DAC}\quad 2}} - {2^{2} \cdot {\hat{V}}_{{DAC}\quad 2}}} \right) + {\Delta\quad{V \cdot {PN}}}}\end{matrix} & (23)\end{matrix}$

For capacitor mismatch of ±0.2% and opamp DC gain of 60 dB we find that:G₂2²·(1+ε·2⁻⁷)   (24)Where ε is between −1 and +1.

The estimated value {circumflex over (V)} is equal to V-Q(V) where Q(V)is the quantization error between the backend ADC and the ADC formedfrom stage 2 and the same backend or the error between the estimatedoutput {circumflex over (V)}_(z,999) of SDAC of stage 2 and V_(z,999) .Also Var[Q(V)] Var[V]/2^(2h) where the precision of the backend is10-bit.

From eq. (23), the variance σ_(z,999) ² of the output of the averager Δecan be estimated by: $\begin{matrix}{\sigma_{\Delta\quad e}^{2} = {\frac{1}{2^{10}N}\sigma_{D{\lbrack{Vol}\rbrack}}^{2}}} & (25)\end{matrix}$

Thus the number of samples needed without this signal subtraction isdivided by 2^(z,999 0). That means, for ADC with 14-bit resolution,instead of requiring a number of 2³⁰ iterations now only 2²⁰ iterationsare sufficient. That shortens the calibration cycle by 1000.

After calibration of stage 2, stage 1 is calibrated using the samemanner. The residue obtained from the stage 1 in the normal operation ofthe ADC is given by:V _(res1) =G ₁·(V _(in) −V _(DAC1))+ΔV·PN   (26)

Again to reduce the variance of the G₁·(V_(z,999) −V_(DAC1)) the terrnV_(z,999) could be estimated using the already calibrated stage 2 andthe following stages but that means that stage 2 need to run at doublespeed and that is not desirable. Instead the same backend used topredict V_(z,999) is now used to predict V_(in) as shown in FIG. 7. Thecontrol signal (cal) switches the input of the backend to the input ofthe stage 1. The other term V_(DAC1) is replaced by estimated value fromSADC of stage 1 obtained during the normal operation.

As described above, global gain correction GGC equalizes the gainmismatch in the channels of TIADC's. For offset mismatch compensation, achopper-based background calibration is known in the art, for example inS. M. Jamal, D. Fu, S. H. Lewis, and P. J. Hurst, “A 10-bit 120 Msample/s time-interleaved analog-to-digital converter with digitalbackground calibration,” IEEE J. Solid-State Circuits, vol. 37, pp.1618-1627, December 2002. In this method, the input signal is convertedto a white signal by a random chopper at the input. The output for eachchannel will contain little information at DC in addition to the offsetand then a low-pass filter is used to extract the offset from everychannel. The extraction of the offset is inaccurate especially when afull-scale input signal is spread so its power at DC is significant. Toaccelerate the extraction cycles the same backend used to shorten thecalibration cycles for the ADC linearity could be used to predict theinput signal before chopping as shown in FIG. 12. Thus instead oflow-pass filtering the ADC output given by:D[V _(c1) ]=V _(in1) ·P _(N1) +V _(ox1)   (27)the offset is extracted from the output given by:D[V _(c1) _(—) _(new)]=(V _(in1) −{circumflex over (V)} _(in1))·P_(N1)+V _(z,999) ·P _(N1) +V _(os1)   (28)where V_(z,999) is the offset of the backend ADC and {circumflex over(V)}_(in1) is the input signal estimated by the ADC's backend. Thoughthe backend offset will be spread and it may have some component at DCbut this spreading will slightly influence the offset extractingcompared to the case where the full-scale analog input V_(in1) is spreadand that will accelerate greatly the calibration cycles.

RESULTS

Simulations have been performed to verify the effectiveness of thesebackground calibration techniques on a 14-bit pipelined ADC. This ADChas two 2.5-bit front-end stages and a backend pan of nine 1.5-bitstages. A capacitor mismatch of ±0.2%, comparator offsets of ±V_(R)/10,and opamp DC gain of 60 dB were used in all the stages. The referencevoltages for each flash sub-ADC and the calibration voltages circuitwere generated by a simulated resistor ladder wherein each resistancewas chosen with a random error of ±0.2% standard deviation. Only the 2front-end 2.5-bit stages were calibrated. Without any specialconsideration to shorten the calibration cycles a number of samplesaround 2³¹ for the coefficients measurement (K=8) were needed. When thebackend ADC and the SADC of the stage under calibration are used toshorten the calibration duration, the number of samples are shortened to2²¹. A similar number of samples were needed when the input signal wassupposed to have 0 power at fs/2 frequency and when the coefficient tobe measured were shifted at this frequency.

A sinewave slightly lower that the full-scale signal around 1/20 thesampling frequency (f_(s)) was applied to the input of the 14-bit ADCbefore and after calibration. The signal-to-noise-and-distortion ratio(SNDR) is 64 dB resulting in an effective number of bits (ENOB) of 10.3bits, and the spurious free dynamic range (SFDR) is 68.4 dB. The SNDRbecomes 84 dB resulting an ENOB of 13.7 bits, and the SFDR is increasedto 98 dB.

A 2-channel time-interleaved ADC was simulated before and after GGC. The2 channels have the same configuration of the one used in the foregoingsimulation and that were already calibrated by the proposed method andoffset mismatch subtracted by shortening the calibration cycles asdescribed above. Before GGC, the SNDR was 71 dB resulting an effectivenumber of bits ENOB of 11.5 bits, and the SFDR was 74 dB. The SNDRbecame 82 dB resulting in an ENOB of 13.3 bits, and the SFDR wasincreased to 91 dB.

It will be appreciated that in the above described embodiments, there isprovided a digital background calibration technique to compensate forthe nonlinearity and the interstage gain error of the internal SDAC,amplifier finite DC gain and reference voltage inaccuracy inmulti-bit/stage pipelined ADC. By injecting subtractive imprecisevoltages (SIV) in a modified conventional multi-bit multiplyingdigital-to-analog converter (MDAC) and performing correlation basedsuccessive coefficient measurements (SCM), a background calibration isperformed. Global gain correction of the ADC is also provided, and it isfeasible to shorten the calibration duration. Simulation resultsdemonstrate the effectiveness, of the above embodiments.

It will also be appreciated that the invention is not limited tocalibration of components in an MDAC, but can be applied to othercircuits in which the output of a first circuit or stage in which thecomponents to be calibrated are found is measured by a second circuit orstage. It will also be appreciated that the invention can be used tocalibrate a voltage reference to be used in a precise-voltage basedapplication circuit.

Calibration of a Voltage Reference

In the embodiment of FIG. 8C, the invention is used to calibrate avoltage reference using the already calibrated pipelined ADC, so that aprecision-voltage circuit 65 can make use of the calibration of thevoltage reference.

In this embodiment, the ratio of the resistances in a string-resistor 60used to calibrate the ADCs or used by any other circuits integrated inthe same chip is identified. To simplify the teaching of thisembodiment, the string resistance 60 presented in FIG. 9 is redrawn inFIG. 13 with K=4 and equation 16 is rewritten as follows:g ₁ =G _(A)·(V _(R3)−(C ₄ /C _(f))·V _(R))   (29.1)g ₂ =G _(A)·(V _(R3)−(C ₄ /C _(f))·V _(R2))   (29.2)g ₃ =G _(A)=(V _(R1)−(C ₄ /C _(f))·V _(R2))   (29.3)g ₄ =G _(A) ·V _(R1)   (29.4)

The term G_(A)(C₄/C_(f))V_(n) is obtained independently from theresistance values using:G _(A)(C ₄ /C _(f))V _(R) =−g ₁ +g ₂ −g ₃ +g ₄   (30)

Now by repeating the eqs (29) by choosing the voltages in the mannerwritten in the following equations:g ₁ =G _(A)·(V _(R)−(C ₄ /C _(f))·V _(R3))   (31.1)g ₂ =G _(A)·(V _(R2)−(C ₄ /C _(f))·V ₃)   (31.2)g ₃ =G _(A)·(V _(R2)−(C ₄ /C _(f))·V _(R1))   (31.3)g ₄ =−G _(A)·(C ₄ /C _(f))·V _(R1)   (31.4)

The term G_(A)·V_(R) is obtained by:G _(A) ·V _(R) =g ₁ −g ₂ +g ₃ −g ₄   (32)

By replacing (32) in (29.1) we obtain G_(A)·Y_(R3) which is the neededV_(R3) multiplied by G_(A).

Now by dividing G_(A)·V_(R3) by (32) we obtain V_(R3)/V_(R)=a (33)independently from G_(A).

By replacing (31.4) in (31.3) we obtain G_(A)·V_(R2)=g₃−g₄.

Now by dividing G_(A)·V_(R2) by (32) we obtain V_(R2)/V_(R)=b (34)independently from G_(A).

From (29.4) we have G_(A)·V_(R1). Again by dividing The latter value by(32) we obtain V_(R1)/V_(R)=c (35).

It will now be shown how to find a digital ratio between V_(R) andV_(Rt) . . . i∈{1,2,3}, as performed by the Resistor/Voltage RatioEstimator 62 shown in FIG. 8C.

The equations (33)-(35) can also be used directly to obtain theresistances values compared to R_(T)=R₁+R₂+R₃+R₄ by using the followingequations.R ₁ /R _(T) =c   (36)(R ₁ +R ₂)/R _(T) =b then R ₂ /R _(T) =b−c   (37)(R ₁ +R ₂ +R ₃)/R _(T) =c then R ₃ /R _(T) =a−b   (38)

To obtain R_(a)/R_(T) we can switch the left side of R₁, in FIG. 1.a, toV_(R) and the right side of R₄ to the ground and compute (29.4) againas:g _(4-new) =G _(A) ·V _(R1-new)   (39)

By dividing (39) by (32) we obtain V_(R1-new)/V_(R)=R₄/R_(T)=d (40).

Moreover, we can find all the resistance compared to R₁ as:R ₂ /R ₁=(b−c)/c   (41)R ₃ /R ₁=(a−b)/c   (42)R ₄ /R ₁ =d/c   (43).

The equations (33-35) can be used to trim the voltage values compared toV_(R). In addition (36-38) or (41-43) can be used to trim the ratiobetween the resistances.

This string-resistance can be used in different applications such asresistor-string-DAC (FIG. 14) and R/2R-DAC (FIG. 15) or any othercircuits that relies on high precision resistances and referencevoltages. In the case of a resistor-string-DAC and R/2R-DAC the trimmingof the resistance values is carried out without interrupting theoperation of the DACs.

Since, the sting-resistances are available for the DAC's usage and theCalibrating ADC (calibrated using the method of the preferredembodiment), digital values corresponding to a,b,c, . . . etc are usedto modify the digital input b₁ the DAC (see FIG. 15) by correctivedigital coefficients to compensate the non-linearity in the DAC-analogoutput due to the resistor mismatch.

In other applications, such as operational amplifier, gain stage orfilter (see FIG. 16), the string resistances are not available to normaluse and calibration. In this case, control switches c₁, c₂ are used toconfigure the circuits between the calibration phase and the normaloperation phase. For instance when c₁=1 and c₂=0 the string resistanceis configured in trimming mode. When c₁=0 and c₂=1 the circuit isconfigured in the normal operation mode.

Also, the reference voltages used in the injection could be generatednot only from string resistance but also from reference voltages ofdifferent analog blocks 66 (see FIG. 8C) that their outputs willconverted to digital values after signal processing. Digitalcoefficients could be found to take into consideration the mismatchbetween these voltages V_(R1),V_(R2) and V_(R) in order to compensatethe effect of the reference voltage mismatch.

Also, passive trimming is not exclusive for resistor-based circuits.Capacitive based circuits could be calibrated also. For instance, thevoltage used in this subtractive injection could be generated directlyfrom a charge capacitive DAC, as shown in FIG. 17. In this case, the DACoutput V_(p) can be used instead of V₁ and V₂ in order to findcorrective coefficient to compensate the DAC-nonlinearity due to thecapacitor mismatch.

It will be appreciated that these equations can be used not only todetermine the ratio of the resistances or voltages in the digital domainbut also to trim the resistances or the capacitors values in a feedbackmanner using an adaptive algorithm (e.g. LMS). A matrix of passiveelement is used in parallel of the passive element used in the circuitto perform the trimming in the analog domain as shown in FIG. 18.

First the difference between voltage to be trimmed V_(R1)(R₂) and V_(R)is found using the Background Calibrated ADC as G_(A)·(V_(R−V)_(R1)(n)). The latter term is divided by G_(A)·V_(R) and subtracted fromthe desired value (V_(R)−V_(R1) _(—) _(z,999) )/V_(R). An error signale(n) is used to update the coefficients of an LMS filter. The negativefeedback in the circuit will help the convergence ofG_(A)·(V_(R)−V_(R1)(n)) to the desire value (V_(R)−V_(R1) _(—) _(z,999))/V_(R).

Calibration of a Sample and Hold Circuit in a Flash ADC

The invention can be applied to calibrate other circuits such as asample-and-hold (S/H) circuit to correct gain error, for example. Aprior art S/H is shown in FIG. 19 where the output voltage is given by:$\begin{matrix}{V_{a} = {{\frac{1}{1 + {1/{Af}}} \cdot \frac{C_{1}}{C_{f}} \cdot V_{1}} = {G_{A} \cdot G_{C} \cdot V_{1}}}} & (44)\end{matrix}$

Gain error correction due to capacitor and finite op-amp gain isessential for S/H's, especially when they are used in time-interleavedapplications.

For calibration purposes, the front-end S/H circuit according to thisembodiment of the invention is changed as shown in FIG. 20. In thiscase, there is no need to add a capacitor to perform voltagesubtraction. Instead, the sign of the input signal V₁ is monitored usinga comparator and a voltage equal to V_(R) is injected without affectingthe dynamic range of the S/H as shown in FIG. 21 a. Here, V₁ is chosento be equal to ground and V₂=sign(V₁)·V_(R) where sign(V₁)=−1 when V₁ ispositive and sign(V₁)=1 when V₁ is negative. In this case, the S/Houtput will be given by:V _(o) =G _(A)·G_(C)·(V ₁ −PN·sign(V ₁)·V _(R))   (45)

Using one comparator to compare V₁ with the ground and to find sign(V₁)may lead to distortion in the S/H transfer function when the comparatoris not accurate as shown in point A in FIG. 21 b where V_(o) exceeds thereference voltage V_(R). Therefore, instead of using an accuratecomparator, two imprecise comparators are used. One comparator comparesV₁ with $- \frac{V_{R}}{4}$and the other compares V₁ with $\frac{V_{R}}{4}$Thus, the voltage V₂ is chosen equal to sign(V₁)·V_(R) when$V_{1} \geq {\frac{V_{R}}{4}\quad{or}\quad V_{1}} \leq {- {\frac{V_{R}}{4}.}}$Otherwise, V₂ is chosen equal 0 by forcing PN to be 0 (see FIG. 21 c).In this case, an offset in every comparator as large as$\frac{V_{R}}{4}$is tolerated without overloading the S/H output.

The output of the S/H V_(o) is correlated with PN·sign(V₁) in thebackground to extract the gain G_(A)·G_(C) of the S/H. A multiplicationby 1/G_(A)·G_(C) for the final output of the ADC will compensate thegain error resulting from the S/H circuit.

1. A method of background calibrating a circuit to be calibrated havinga plurality of circuit elements and providing an output residue, themethod comprising: switching one of said circuit elements to besubstituted by an equivalent circuit element within said circuit;injecting at least one calibration signal into at least one of saidcircuit elements, wherein said calibration signal causes a measurablechange in said output residue; measuring said change; calculating acalibration parameter for said circuit based on said change; andperforming a calibration correction to an output of said circuit usingsaid parameter.
 2. The method as claimed in claim 1, wherein saidperforming a calibration correction comprises correcting for saidmeasurable change.
 3. The method as claimed in claim 1, wherein saidoutput residue has a dynamic range for measurement, and said injectingcomprises: providing at least two calibration signals to operate in saidcircuit in a subtractive manner so that said output residue remainswithin said dynamic range; providing a group of different imprecisevoltages for said calibration signals having at least one value thatused alone would cause said residue to lie outside said dynamic rangeand at least one value that used alone would cause said residue to liewithin said dynamic range; selecting a series of different combinationsof ones of said group of imprecise voltages for injection in saidsubtractive manner, said series of combinations including one of saidimprecise voltages to be isolated once, a remainder of said imprecisevoltages each used in two of said different combinations, with one ofsaid different combinations comprising a zero voltage and one of saidimprecise voltages having a value that used alone would cause saidresidue to lie within said dynamic range; and injecting in said circuiteach of said different combinations of said imprecise voltages as saidcalibration signals; said measuring comprising measuring said change foreach of said different combinations, and said calculating saidcalibration parameter comprises calculating, from a sum of said changemeasured for each of said different combinations, a value as a functionof said one of said imprecise voltages to be isolated independently ofsaid remainder of said imprecise voltages.
 4. The method as claimed inclaim 3, wherein said providing a group of imprecise voltages comprises:providing a string resistance connected at one end to a referencevoltage and to said zero voltage at another end.
 5. The method asclaimed in claim 4, wherein said output residue is essentially an ACsignal, and said change is measured by obtaining an average of saidoutput residue with said calibration signal injected and an average ofsaid output residue without said calibration signal injected, saidchange being a difference between said averages.
 6. The method asclaimed in claim 5, wherein said injecting comprises alternating betweenno injecting and injecting of said calibration signal from measurementto measurement.
 7. The method as claimed in claim 6, wherein saidinjecting alternates in a random or pseudorandom manner, whereby saidaverages are free of aliasing.
 8. The method as claimed in claim 5,wherein said circuit is a pipelined ADC comprising a plurality ofstages, said measuring being performed using said stages downstream ofone of said stages whose circuit elements are being calibrated, saidmagnitude of said measurable change being small enough such that saidoutput residue is within a dynamic range of said downstream stages. 9.The method as claimed in claim 8, wherein said reference voltage is usedin at least one sub-DAC of said pipelined ADC.
 10. The method as claimedin claim 2, wherein said residue occupies an identified frequency rangeduring normal operation, said injecting comprises alternating between noinjecting and injecting of said calibration signal from measurement tomeasurement at a frequency resulting in said measurable change having afrequency outside of said frequency range, and said measuring comprisesfiltering said residue to detect said change at said frequency outsideof said frequency range.
 11. The method as claimed in claim 10, furthercomprising detecting said identified frequency range, determiningwhether there is a suitable said frequency resulting in said measurablechange having a frequency outside of said frequency range, and if notsaid change is measured by obtaining an average of said output residuewith said calibration signal injected and an average of said outputresidue without said calibration signal injected, said change being adifference between said averages, said injecting alternating in a randomor pseudorandom manner, whereby said averages are free of aliasing. 12.The method as claimed in claim 8, wherein said residue occupies anidentified frequency range during normal operation, said injectingcomprises alternating between no injecting and injecting of saidcalibration signal from measurement to measurement at a frequencyresulting in said measurable change having a frequency outside of saidfrequency range, and said measuring comprises filtering said residue todetect said change at said frequency outside of said frequency range.13. The method as claimed in claim 12, further comprising detecting saididentified frequency range, determining whether there is a suitable saidfrequency resulting in said measurable change having a frequency outsideof said frequency range, and if not said change is measured by obtainingan average of said output residue with said calibration signal injectedand an average of said output residue without said calibration signalinjected, said change being a difference between said averages, saidinjecting alternating in a random or pseudorandom manner, whereby saidaverages are free of aliasing.
 14. The method as claimed in claim 8,wherein said pipelined ADC comprises at least three stages and a backendstage of said pipelined ADC operates at a multiple of a frequency ofsaid ADC, said backend stage being used to measure said change in saidoutput residue of a plurality of stages.
 15. The method as claimed inclaim 2, wherein said calibration correction is a global correctionconsistent with other circuits operative with said circuit to becalibrated.
 16. The method as claimed in claim 8, wherein saidcalibration correction is a global gain correction consistent with othercircuits operative with said circuit to be calibrated, said calibrationparameter comprising a transfer characteristic gain of said ADC to becalibrated, said global gain correction comprising dividing a finaldigital output of said ADC to be calibrated by transfer characteristicgain.
 17. The method as claimed in claim 16, wherein said pipelined ADCcircuit to be calibrated is one of a group of time-interleaved ADCcircuits, said calibration correction reducing gain mismatch acrosschannels of said group.
 18. A method of calibrating a voltage reference,the method comprising: a) providing a first circuit having a pluralityof calibrated circuit elements and generating an output residue having adynamic range for measurement, said calibrated circuit elements having aknown value; b) providing at least two calibration signals to operate insaid first circuit in a subtractive manner so that said output residueremains within said dynamic range; c) providing a group of differentimprecise voltages for said calibration signals having at least onevalue that used alone would cause said residue to lie outside saiddynamic range and at least one value that used alone would cause saidresidue to lie within said dynamic range; d) selecting a series ofdifferent combinations of ones of said group of imprecise voltages forinjection in said subtractive manner, said series of combinationsincluding one of said imprecise voltages to be isolated once, aremainder of said imprecise voltages each used in two of said differentcombinations, with one of said different combinations comprising a zerovoltage and one of said imprecise voltages having a value that usedalone would cause said residue to lie within said dynamic range; e)injecting in said first circuit each of said different combinations ofsaid imprecise voltages as said calibration signals; f) measuring saidchange for each of said different combinations; and g) calculating, froma sum of said change measured for each of said different combinations, avalue that is a function of said one of said imprecise voltages to beisolated independently of said remainder of said imprecise voltages. 19.The method as claimed in claim 18, wherein said providing a group ofimprecise voltages comprises: providing a string resistance connected atone end to a reference voltage and to said zero voltage at another end.20. The method as claimed in claim 19, wherein steps (c) through (g) arerepeated to identify a ratio of resistances in said string resistance.21. The method as claimed in claim 18, wherein said first circuitcomprises circuitry that outputs as said residue a difference betweensaid calibration signals, said reference value being said valuecalculated in step (g) that is equal to said one of said imprecisevoltages to be isolated.
 22. The method as claimed in claim 19, furthercomprising; switching one of said circuit elements in said first circuitreceiving one of said calibration signals to be substituted by anequivalent circuit element within said circuit; and correcting for saidmeasurable change in an output of said first circuit; wherein saidcalibrating is performed in the background during normal operation ofsaid first circuit.
 23. The method as claimed in claim 22, wherein saidoutput residue is essentially an AC signal, and said change is measuredby obtaining an average of said output residue with said calibrationsignal injected and an average of said output residue without saidcalibration signal injected, said change being a difference between saidaverages.
 24. The method as claimed in claim 23, wherein said injectingcomprises alternating between no injecting and injecting of saidcalibration signal from measurement to measurement.
 25. The method asclaimed in claim 24, wherein said injecting alternates in a random orpseudorandom manner, whereby said averages are free of aliasing.
 26. Themethod as claimed in claim 22, wherein said first circuit is a pipelinedADC comprising a plurality of stages, said measuring being performedusing said stages downstream of one of said stages whose circuitelements are subject to said injecting, said magnitude of saidmeasurable change being small enough such that said output residue iswithin a dynamic range of said downstream stages.
 27. The method asclaimed in claim 18, wherein said group of imprecise voltages comprisesmore than five imprecise voltages.
 28. The method as claimed in claim18, wherein said residue occupies an identified frequency range duringnormal operation, said injecting comprises alternating between noinjecting and injecting of said calibration signal from measurement tomeasurement at a frequency resulting in said measurable change having afrequency outside of said frequency range, and said measuring comprisesfiltering said residue to detect said change at said frequency outsideof said frequency range.
 29. The method as claimed in claim 28, furthercomprising detecting said identified frequency range, determiningwhether there is a suitable said frequency resulting in said measurablechange having a frequency outside of said frequency range, and if notsaid change is measured by obtaining an average of said output residuewith said calibration signal injected and an average of said outputresidue without said calibration signal injected, said change being adifference between said averages, said injecting alternating in a randomor pseudorandom manner, whereby said averages are free of aliasing. 30.The method as claimed in claim 26, wherein said residue occupies anidentified frequency range during normal operation, said injectingcomprises alternating between no injecting and injecting of saidcalibration signal from measurement to measurement at a frequencyresulting in said measurable change having a frequency outside of saidfrequency range, and said measuring comprises filtering said residue todetect said change at said frequency outside of said frequency range.31. The method as claimed in claim 30, further comprising detecting saididentified frequency range, determining whether there is a suitable saidfrequency resulting in said measurable change having a frequency outsideof said frequency range, and if not said change is measured by obtainingan average of said output residue with said calibration signal injectedand an average of said output residue without said calibration signalinjected, said change being a difference between said averages, saidinjecting alternating in a random or pseudorandom manner, whereby saidaverages are free of aliasing.
 32. The method as claimed in claim 26,wherein said pipelined ADC comprises at least three stages and a backendstage of said pipelined ADC operates at a multiple of a frequency ofsaid ADC, said backend stage being used to measure said change in saidoutput residue of a plurality of stages.
 33. Amultiplying-digital-to-analog (MDAC) circuit for use in a backgroundcalibrated pipelined analog-to-digital (ADC) circuit, the MDACcomprising: a plurality, n, of inputs from a sub-digital-to-analogconverter (SDAC); an amplifier; a feedback capacitor and switches forconnecting said feedback capacitor in a first state between ground and afirst modulated voltage, and in a second state between an input of saidamplifier and an output of said amplifier; a switch matrix having aplurality, n+1, of outputs for controllably directing, in response to acontrol signal, said inputs from said SDAC and a second modulatedvoltage; and a plurality, n+1, of summing capacitors connected on oneside to said input of said amplifier and connected on another side, insaid first state, via switches to a stage input voltage and, in saidsecond state, via switches to an output of a corresponding one of saidswitch matrix outputs.
 34. The MDAC as claimed in claim 33, wherein saidswitch matrix comprises a plurality, n+1, of multiplexers, wherein n ofsaid multiplexers have one input connected to a corresponding one ofsaid inputs from said SDAC, and an (n+1)th one of said multiplexers hasan input from each of said inputs from said SDAC, said multiplexers eachhaving an input from said second modulated voltage, and providing acorresponding one of said switch matrix outputs.
 35. A method ofbackground calibrating a pipelined ADC circuit to be calibrated having aplurality of circuit elements and providing an output residue, themethod comprising: injecting at least one calibration signal into atleast one of said circuit elements of a stage of said ADC undercalibration, wherein said calibration signal causes a measurable changein said output residue of said stage; predicting a value of said outputresidue of said stage without said injecting; using a backend ADC ofsaid pipelined ADC to measure an output residue of a stage upstream ofsaid stage under calibration, and predicting a value of a sub-DAC outputof said stage under calibration; measuring said change using said outputresidue of said stage under calibration using said backend ADC, saidpredicted value of said output residue of said stage without saidinjecting, and said predicted value of said sub-DAC output of said stageunder calibration; calculating a calibration parameter for said circuitbased on said change; and performing a calibration correction to anoutput of said circuit using said parameter.
 36. The method as claimedin claim 35, wherein said measuring comprises obtaining an average ofsaid comparison of said output residue with said predicted value.
 37. Amethod of background calibrating a circuit to be calibrated having aplurality of circuit elements and providing an output residue, saidresidue occupying an identified frequency range during normal operation,the method comprising: injecting at least one calibration signal into atleast one of said circuit elements of said circuit, wherein saidcalibration signal causes a measurable change in said output residue ofsaid stage, and alternating between no injecting and injecting of saidcalibration signal from measurement to measurement at an injectionfrequency resulting in said measurable change having a frequency outsideof said frequency range; detecting said identified frequency range, andsetting said injection frequency such that said measurable change has afrequency outside said identified frequency range; filtering saidresidue to detect said change at said frequency outside of saidfrequency range; calculating a calibration parameter for said circuitbased on said change; and performing a calibration correction to anoutput of said circuit using said parameter.
 38. The method as claimedin claim 37, wherein when there is no suitable said injection frequencyresulting in said measurable change having a frequency outside of saidfrequency range, then said change is measured by obtaining an average ofsaid output residue with said calibration signal injected and an averageof said output residue without said calibration signal injected, saidchange being a difference between said averages, said injectingalternating in a random or pseudorandom manner, whereby said averagesare free of aliasing
 39. The method as claimed in claim 38, wherein saidcircuit is a pipelined ADC circuit, and said filtering comprises using abackend ADC of said pipelined ADC to measure said filtered residue.